The invention relates to semiconductor devices and in particular, to semiconductor devices in which short channel effects are minimized.
Recently, techniques for lowering the resistance of gate source and drain regions have been necessary for the high speed operation of very large scale integration (VLSI) devices. Polycide structures for use as gate portions and silicide structures for lowering the resistance of the gate source and drain regions have been developed. However, in general, polysilicon beneath silicide is of the N.sup.+ type only and connection with the substrate is accomplished only on the N channel side.
Since the polycide consists of two layers, even though polysilicon beneath silicide is provided on both P and N channel regions having different polarities, the P and N channels are connected at the upper silicide. Furthermore, when the P and N channels are simultaneously formed by contact self-alignment, it is possible to connect the drain regions of the P and N channels to adjacent transistors. It, therefore, becomes possible to lower the resistance of the gate, source and drain of the P and N channels and the process of connecting the regions, that is, providing aluminum on the contact portion of the polysilicon between the different polarities of the P and N channel regions, is reduced.
In order to reduce resistor/capacitor, RC delay in gate wiring, conventional N+polysilicon gate materials have been replaced by silicide, polycide and refractory metals. In conventional polycide gates, the P channel is not formed by contact self-alignment because the polysilicon contains N type impurities. It has been necessary to inject boron ions, B.sup.+, into the P channel in order to decrease the differences in work function between the P and N channels and regulate threshold voltage However, injection of boron ions causes punch through voltage to fall.
It is, therefore, desirable to provide a novel semiconductor device in which both the P and N channels are formed by contact self-alignment and which overcomes the defects of prior art semiconductor devices.